The nonvolatile semiconductor memory has an overall configuration, for example, as that shown in FIG. 1. In FIG. 1, N cell blocks 11.sub.1 to 11.sub.N (for example, eight blocks) each having multiple transistor cells are arranged in a row. The cell blocks 11.sub.1 to 11.sub.N are provided with bit line select circuits 12.sub.1 to 12.sub.N and sense amplifiers/sense buffers 13.sub.1 to 13.sub.N respectively.
A row address signal is supplied from a row address buffer to each of the cell blocks 11.sub.1 to 11.sub.N via a row decoder 15. A column address signal is supplied from a column address buffer 16 to each of the bit line select circuits 12.sub.1 to 12.sub.N via a column address decoder 17. A voltage V.sub.S sent from a source power supply circuit 18 is applied to each of source electrodes of the transistor cells of the cell blocks 11.sub.1 to 11.sub.N.
FIG. 2 shows the cell block 11, one of the cells blocks in the aforesaid nonvolatile semiconductor memory, and its peripheral circuitry. In FIG. 2, components identical to those in FIG. 1 bear the same reference numerals, of which a description will be omitted. In FIG. 2, the bit line select circuit 12 comprises n-channel MOS field-effect transistors Q1 to Qn. Column address signals Y1 to Yn are fed from the column decoder 17 to the gates of the transistors Q1 to Qn.
The cell block 11 comprises a total of n by n field-effect transistors Q11 to Qnn having floating gates and control gates. The gates of n transistors Qil to Qin (where, i=1, 2, etc., and n) arranged in tandem are provided with row address signals Xi sent from the row decoder 15 via word lines.
The drains of the n transistors Qli to Qni arranged in tandem are connected to the drains of the transistors Qi in the bit line select circuit 12 via bit lines. Voltage from the source power circuit 18 is applied to each of the sources of the transistors Qll to Qnn. A cell amplifier 13a and a write buffer 13b are connected to each of the sources of the transistors Q1 to Qn.
In the foregoing semiconductor memory, when row addresses Xi and column addresses Yi are selected for writing, data read from the write buffer 13 are written in the transistors Qij of the cell blocks 11.sub.l to 11.sub.N. Writing is performed simultaneously on one bit per each of the cell blocks 11.sub.1 to 11.sub.N or a total of N bits designated with the row addresses and column addresses. Data erasing is performed concurrently on all transistors in the cell blocks 11.sub.1 to 11.sub.N.
In a flash memory, information is retained depending on the presence or absence of a charge in a memory cell. FIG. 3 shows an example of a structure of a memory cell. As shown in FIG. 3, a gate has a two-layered structure consisting of a control gate (CG) 25 and a floating gate (FG) 24. The control gate 25 is connected to a word line WLi and a drain (D) 23 is connected to a bit line BLi. Reference numeral 26 denotes a tunneling oxide film.
The flash memory is broadly divided into two types of what are referred to as NOR and NAND. These types differ from each other in a method of writing, reading, or erasing information into or from a memory cell. Taking the NOR type flash memory as an example, writing, reading, or erasing information into or from a memory cell will be described below.
When information is to be written in a memory cell having the aforesaid structure, as shown in FIG. 4, the word line WLi is set to Vpp (approx. 12 V), the bit line BLi is set to approx. 6 V, and the source S is set to 0 V. High voltage is then applied to the control gate CG and drain D. Current then flows into the memory cell. Part of the electrons flowing through the memory cell are accelerated due to the high electric field in the vicinity of the drain D, gain energy, and then goes beyond the energy barrier of an insulating film of the floating gate. The electrons are finally injected into the floating gate FG. The floating gate FG is not electrically coupled with other circuits, so it therefore can retain charges on a semi-permanent basis.
When information is to be read from a memory cell, as shown in FIG. 5, the word line WLi is set to Vcc (about 5 V), the bit line BLi is set to about 1 V, and the source S is set to 0 V. The memory cell is then selected by specifying the word line WLi and bit line BLi. The threshold value of the cell transistor varies depending on the charges retained in the floating gate FG. Current flowing through the selected memory cell varies depending on the information stored therein. The information therefore can be read out by detecting and amplifying the current.
The voltage levels of the control gate CG, drain D, source S, and substrate PS in the aforesaid operative states are set to the values listed in Table 1.
TABLE 1 ______________________________________ Voltages in modes in a prior art CG D S PS ______________________________________ Reading Vcc to 1 V 0 V 0 V Writing Vpp to 6 V 0 V 0 V Erasing 0 V Float Vpp 0 V ______________________________________
When information is to be erased from a memory cell, as shown in FIG. 6, the word line WLi is set to about 0 V and the bit line BLi is opened. In this state, the drain D is opened, about 0 volt is applied to the control gate CG, and a high voltage of about 12 volts is applied to the source S.
Since a high voltage is applied to the source S, deep diffusion is required in order to increase the resistivity of the diffused layer in the source. This hinders reduction in cell area.
For divided erasing, it is required that the Vss line in the source must partly have a different voltage. This leads to disconnection or an increased number of drive circuits. Eventually, chip size increases.
A solution to the above problem is to apply a negative voltage to the word line WLi. To be more specific, as shown in FIG. 7, a negative voltage (about -10 V) is applied to the control gate CG and Vcc (about 5 V) is applied to the source S. The drain D is opened. Erasing is then executed.
In this case, since a low voltage is applied to the source S, the resistivity of the source need not be intensified. This contributes to reduction in cell size. Partial erasing is enabled by selectively applying negative voltage to the control gates CG.
The aforesaid erasing method is a source erasing method in which charges in the floating gate FG are routed to the source. A channel erasing method is also available, wherein charges in the floating gate are routed to a channel; that is, a substrate. Even in this method, negative voltage is applied to the control gate. The channel erasing method is sometimes employed for the aforesaid NAND-type flash memory.
FIGS. 8 to 11 show the states of a memory cell with voltage applied according to various erasing methods. In FIGS. 8 to 11, the memory cell is an n-channel transistor.
FIG. 8 shows a state in which positive voltage is applied according to a channel erasing method. The drain D and source S are opened, and the control gate CG is set to 0 V. The high voltage Vpp is applied to the P well equivalent to a channel. In channel erasing, a triple-well structure shown in FIG. 8 is adopted because positive bias is applied to the channel.
FIG. 9 shows a state in which a positive voltage is applied according to the source erasing method. The drain D is opened, and then the control gate CG is set to 0 V. The high voltage Vpp is applied to the source S. The substrate is opened or set to 0 V.
FIG. 10 shows a state in which a negative voltage is applied according to the channel erasing method. The drain D and source S are opened, and the control gate CG is set to a negative voltage V.sub.BB. A positive voltage Vcc is applied to the p well equivalent to a channel. V.sub.BB -Vcc is applied between the control gate CG and channel.
FIG. 11 shows a state in which negative voltage is applied according to the source erasing method. The drain D is opened, and then the control gate CG is set to the negative voltage V.sub.BB. The source S is set to the positive voltage Vcc.
The methods for erasing a flash memory which have been described so far, have lots of problems with actual erasing. The problems will be described below.
Erasing of a flash memory is either concurrent erasing, in which all memory cells are erased concurrently, or block-by-block erasing in which erasing is performed block by block. Some of the memory cells to be erased concurrently contain data, while other cells do not contain data. In other words, some cells hold electrons in their floating gates, while other cells do not. If erasing is performed on a memory cell in which no electrons are held, a state in which too many electrons are extracted (that is, a state in which holes are injected) is set up. This is referred to as excessive erasing. When excessive erasing occurs, a "Normally On" state in which a memory cell is on even during normal operation is established disabling normal operation. Pre-erase writing is then performed, wherein data are written in all memory cells before erasing is done. The time required for erasing therefore includes the time required for pre-erase writing. In order to reduce the erasing time, the time required for pre-erase writing must be diminished.
In erasing a flash memory, whichever is adopted; channel erasing or source erasing, voltage applied between the control gate CG and channel or source S greatly affects the erasing. For stable erasing, the voltage to be applied between the control gate and the channel or source must be held constant irrelevant of the fluctuation in external power supply. A memory for a portable device is one of currently conceivable application fields for a flash memory. This kind of portable equipment use batteries as a power supply. When employed for portable equipment, a flash memory is therefore subjected to a voltage fluctuation in an external power supply. Under these circumstances, there is an increasing demand for an erasing method for a flash memory that permits stable erasing irrelevant of a fluctuations in an external power supply, and for a flash memory that can be erased according to the erasing method.
Furthermore, when the source erasing method is employed, the foregoing fluctuation in external power supply may cause the voltage that is applied from a source to vary, or the characteristics of memory cells or drive circuits to differ from one another. As a result, the electric field in the source region becomes stronger and avalanche current increases. When the avalanche current flows, the memory cells deteriorate. Consequently, the rewritable frequency of a flash memory decreases or memory cells are destroyed.
The foregoing problems relate to the principle of erasing. The circuitry in a flash memory for performing the aforesaid erasing has several problems; such as, how to downsize the circuitry, reduce power consumption, or speed up processing.
As mentioned above, the resistivity of a junction in a source region can be improved by applying negative voltage to a control gate during erasing. This has the advantage of enabling reduction of a cell area. It is, however, a big problem how to realize application of negative voltage to the control gate.
It is, for example, conceivable to apply negative voltage from a row decoder to word lines. The voltage to be applied to a word line is changed depending on whether the word line is selected or not. In a flash memory, the voltage to be applied to a word line must be varied depending on whether the read mode or write mode is selected. When the row decoder is used to apply a negative voltage, the voltage to be applied to a word line must be changed to a negative voltage. A word line selected in the read or write mode has a higher voltage than other unselected word lines. For erasing, however, the selected word line must have a lower voltage than the unselected word lines. The level of applied voltage must therefore be reversed depending on the logic of selected or unselected word lines. This results in complex circuitry, making downsizing in possible.
A flash memory includes an internal power switching circuit for switching supply voltages depending on a mode. A conventional internal power switching circuit has a simple circuitry but is likely to cause a latch-up phenomenon. The switching speed is decreased in order to avoid the latch-up phenomenon. This contradicts efforts to speeding up processing.
Furthermore, for negative voltage erasing, bias voltage must be applied to a substrate or part of a well. A conventional substrate bias circuit is realized with a p-channel depletion-type transistor. The manufacturing process is complex and downsizing is hard to do.
Moreover, in a flash memory, the logic of a word line, selected or unselected, must be reversed depending on whether the erase mode or any other mode is specified. An exclusive-OR circuit is employed for the logical reversal. This circuit is also complex, posing an obstacle to downsizing.
DISCLOSURE OF THE INVENTION
The present invention attempts to solve the aforesaid problems, and has the following objects:
(1) To speed up an erasing operation including a pre-erase writing operation;
(2) To enable stable erasing for a specified period of time;
(3) To prevent deterioration of memory cells and increase rewritable frequency;
(4) To minimize the negative effect of excessive erasing by suppressing the influence of excessive erasing of a certain memory cell on other memory cells;
(5) To realize a simple structure that enables selective application of negative voltage to word lines;
(6) To realize an internal power switching circuit that can operate at a high speed with simple circuitry;
(7) To realize a substrate (well) voltage control circuit that consumes limited power and can be downsized; and
(8) To realize exclusive-OR and exclusive-NOR circuits that can be downsized.
For attaining the object (1), in a flash memory based on the first mode of the present invention, each of multiple word lines is connected to the gates of multiple transistor cells arranged in a row, each of multiple bit lines is connected to the drains of multiple transistor cells arranged in tandem, and data can be written electrically in any transistor cell or data can be erased electrically from all transistor cells concurrently. When data of specified values are written in all transistor cells before data erasing, at least either all the bit lines or all the word lines are selected in units of multiple lines. The data of specified values are then written in multiple transistor cells connected to the selected multiple bit lines or word lines.
In a conventional flash memory, pre-erase writing as well as writing is performed for each memory cell. Therefore, too much time is taken up by this for pre-erase writing. In the flash memory based on the first mode of the present invention, pre-erase writing is performed in units of multiple memory cells. The time required for pre-erase writing can therefore be reduced.
For attaining the object (2), a flash memory based on the second mode of the present invention, which performs channel erasing or source erasing by applying a negative voltage to a control gate, includes a voltage restriction means for restricting the negative voltage to be applied to the control gate so that the negative voltage will be a constant value relative to the voltage of a channel or source, or two voltage restriction means for restricting the negative voltage to be applied to the control gate and the voltage to be applied to the source so that the voltages will be a constant value relative to a common reference voltage.
In the flash memory based on the second mode of the present invention, the voltage between a control gate and a channel or source is held constant all the time, so errors in erasing time will be diminished.
For attaining the object (3), a flash memory based on the third mode of the present invention includes a cell matrix in which rewritable nonvolatile memory cells are arranged at intersections between multiple word lines and multiple bit lines, and a power circuit for feeding a supply voltage to each of the sources of transistors forming the nonvolatile memory cells, and performs source erasing by applying a high voltage to the sources. The power circuit includes a current restriction element that has a specified load characteristic.
In the flash memory based on the third mode of the present invention, the power supply for applying high voltage to the sources of memory cells has a current restriction element. Despite the fluctuation in source voltage, as long as the load characteristics of the current restriction element are defined so that a specified voltage, which is equal to or lower than an avalanche voltage, will be applied, injection of holes during erasing can be suppressed. Deterioration of memory cells is therefore minimized.
For attaining the object (4), in a flash memory based on the fourth mode of the present invention, memory cells are grouped in units of a specified number of memory cells on the same word line, select lines are provided to select a specified memory cell group among the memory cell groups, the gates of MOS transistors are connected to the word lines of the memory cell groups and the sources thereof are connected to the sources of the memory cells in each memory cell group, and the memory cell groups including the MOS transistors are formed in a well. When specified data previously written in the memory cell groups are to be erased electrically, a negative voltage is applied to the word lines.
In the flash memory based on the fourth mode of the present invention, MOS transistors are employed and the gates of the MOS transistors are connected to the word lines of memory cell groups. The sources of the MOS transistors are connected to those of the memory cells of each memory cell group. When data is to be read, since only a selected memory cell group is connected to the sources of the MOS transistors, even if excessive erasing occurs in one cell of unselected memory cell groups, since the sources of the unselected memory cell groups are disconnected, the influence of the excessive erasing can be suppressed.
Complex control is unnecessary for erasing. Moreover, since one MOS transistor is added to each memory cell group, the cell area hardly deviates from that in a conventional memory. Eventually, the negative effect of excessive erasing can be prevented, and an increase in cell size can be minimized.
For attaining the object (5), in a flash memory based on the fifth mode of the present invention, a row decoder outputs the negative voltage to be applied to word lines for erasing. Herein, the row decoder includes drive units for supplying decoded signals to word lines. The drive unit selectively outputs a voltage to be applied to a first power terminal and a voltage to be applied to a second power terminal. The drive unit can enter either a first operation mode in which a first voltage is applied to the first power terminal and a second voltage that is lower than the first voltage is applied to the second power terminal or a second operation mode in which a third voltage is applied to the first power terminal and a fourth voltage that is higher than the third voltage is applied to the second power terminal. Output voltages are thus changed depending on whether the first or second operation mode is selected.
In the flash memory based on the fifth mode of the present invention, the levels of voltages to be applied to the power terminals of a drive unit in a row decoder are varied between two modes; that is, the levels of voltages to be applied to the power terminals of a drive unit in a row decoder are varied depending on which of the modes is specified. This obviates the need of changing the logic of each word line between selected and unselected. Simple circuitry ensues.
In a flash memory based on the sixth mode of the present invention or another mode for attaining the object (5), a row decoder includes a level change circuit comprising a first connection switch element whose first terminal is connected to an input terminal for inputting an input signal and whose second terminal is connected to a first output terminal for outputting a first output signal, a second connection switch element whose first terminal is connected to the input terminal and whose second terminal is connected to a second output terminal for outputting a second output signal, a first inverter whose input terminal is connected to the second terminal of the first connection switch element, whose output terminal is connected to the second output terminal, and whose power terminals are connected respectively to a first voltage line for feeding a desired voltage that is higher than a supply voltage and a second voltage line for feeding a desired voltage that is lower than a ground voltage, and a second inverter whose input terminal is connected to the second terminal of the second connection switch element, whose output terminal is connected to the first output terminal, and whose power terminals are connected respectively to the first voltage line and second voltage line.
In the flash memory based on the sixth mode of the present invention, the level change circuit has the capacity for level change and logic change. A row decoder capable of applying negative voltage selectively to word lines can thus be realized with a small-scale circuitry.
For attaining the object (5), a flash memory based on the seventh mode of the present invention is provided with a negative voltage source independently of a row decoder. The negative voltage source is connected to word lines via a negative voltage bias circuit comprising a capacitor to one end of which a clock pulse is supplied, a first p-channel MIS field-effect transistor whose drain is connected to a negative voltage output terminal and whose gate and source are connected to the other end of the capacitor, and a second p-channel MIS field-effect transistor whose drain is connected to the source of the first p-channel MIS field-effect transistor, whose gate is connected to the negative voltage output terminal, and whose source is provided with negative voltage. When negative voltage is applied, the row decoder outputs a word line application signal whose logic is reversed. A logic circuit extends control so that when a word line application signal whose logical value is low is output, a clock pulse will be fed to the negative voltage bias circuit.
In a flash memory based on the seventh mode of the present invention, the foregoing negative voltage bias circuit is used to control whether or not to apply negative voltage depending on whether or not a clock signal is to be input. The input of a clock signal is controlled by a decoded signal sent from the row decoder, which enables selective application of negative voltage. Although another system independent of the row decoder is employed for negative voltage application, since an existing row decoder is used to select word lines, a simple circuitry ensues. Moreover, downsizing is possible.
The eight mode of the present invention is an internal power switching circuit for use in a flash memory or the like, comprising a first MOS transistor of a first polarity one of whose drain and source electrodes is connected to a first power line and the other of whose drain and source electrodes is connected to a second power line;
a second MOS transistor of a second polarity one of whose drain and source electrodes and whose well are connected to a third power line having a higher voltage than the first power line, and the other one of whose drain and source electrodes is connected to a node; and
a third MOS transistor of the second polarity one of whose drain and source electrodes is connected to the node and the other of whose drain and source electrodes is connected to the second power line. The internal power switching circuit further includes a fourth MOS transistor of the first polarity one of whose drain and source electrodes is connected to the third power line and the other of whose drain and source electrodes is connected to the second power line.
In the internal power switching circuit based on the eighth mode of the present invention, when a low voltage is switched to a high voltage, the fourth MOS transistor assists in boosting the voltage of the second power line. This helps minimize the channel current in the second MOS transistor. A latch-up phenomenon can therefore be avoided.
The ninth mode of the present invention is a substrate (well) voltage control circuit for use in a flash memory or the like. For attaining the object (7), the substrate voltage control circuit comprises a negative voltage source for outputting a negative voltage to a power line connected to a component whose voltage is to be controlled, a first n-channel transistor whose substrate (well) and source are connected to the power line and whose drain is connected to a ground power supply, a second n-channel transistor whose substrate (well) and source are connected to the power line and whose drain is connected to the gate of the first n-channel transistor, a first switch installed between the gate of the first n-channel transistor and a positive power supply, a second switch for use in selecting whether the gate of the second n-channel transistor is to be connected to the positive power supply or ground power supply, or opened, and a capacitative element connected between the gate and source of the second n-channel transistor. When negative voltage is not applied, the negative voltage source is put into a non-output state, the first switch is made, and the second switch is connected to the ground power supply. When negative voltage is to be applied, the first switch is opened and the second switch is connected to the positive power supply at the same time. Thereafter, the second switch is opened and the negative voltage source is put into an output state.
In the substrate (well) voltage control circuit based on the ninth mode of the present invention, when negative voltage is applied, the gate-source voltage of the second n-channel transistor is held at a specified value owing to the charges retained in the capacitative element before switching is done. The second n-channel transistor therefore remains in the on state. The gate of the first n-channel transistor therefore assumes a negative voltage. The first n-channel transistor is then turned off. The power line is then disconnected from the ground power supply. A large voltage will not be applied between the gate and source of the second n-channel transistor, which obviates the need of improving resistivity, and downsizing becomes possible.
The tenth mode of the present invention is an exclusive-OR circuit for use in a flash memory or the like. For attaining the object (8), the exclusive-OR circuit includes a first CMIS inverter in which the source of a first pMIS transistor is connected to a high-voltage power supply line, the source of a first nMIS transistor is connected to a low-voltage power supply line, the gates of the first pMIS transistor and first nMIS transistor are connected to each other to serve as an input terminal, the drains of the first pMIS transistor and first nMIS transistor are connected to each other to serve as an output terminal, a second pMIS transistor whose source is connected to the input terminal of the first CMIS inverter and provided with a first input, and a second nMIS transistor whose drain is connected to the output terminal of the first CMIS inverter, whose source is connected to the drain of the second pMIS transistor, and whose gate is connected to the date of second pMIS transistor and provided with a second input. The exclusive OR of the first and second inputs is output from a contact point between the drain of the second pMIS transistor and the source of the second nMIS transistor.